The present invention relates to high performance semiconductor devices. The increasing microminiaturization of semiconductor integrated circuits has raised lateral semiconductor device density. In turn, this has led to the utilization of lateral electrical isolation. However, many prior art procedures involving recessed oxide isolation provide etched recesses widest at the surface and which tend to taper inwardly, providing a narrowing lateral isolation area with increasing depth, thereby using up an unacceptable width of wafer surface to provide adequate deep electrical isolation.
U.S. Pat. No. 3,972,754 by Riseman describes a process for forming dielectrically isolated regions in a silicon semiconductor substrate in which a recessed silicon dioxide area is formed extending into the substrate using a photolithographic process followed by etching and thermal oxidation. Thereafter, blanket introduction of impurities of conductivity opposite to the conductivity of the silicon substrate surface is carried out into the portions of the substrate surface remaining unoxidized. Then, a layer of opposite-type conductivity is epitaxially deposited (a selective epitaxial process where the epitaxial layer is provided over selective areas of the wafer surface is preferred to improve device density and performance) on the substrate surface. In the art, it is known that the wafer surface must be made more planar prior to growing the epitaxial layer. In particular, the small hump formed where oxide penetrates between the mask used in the photolithographic process and the substrate (the "bird's head" and "bird's beak") must be removed by a planarization technique or the formation thereof prevented by sidewall capping, such as by a layer of nitride. In the remainder of the U.S. Pat. No. 3,972,754 process, regions of recessed oxide are formed extending through the epitaxial layer into registered contact with the regions of recessed silicon dioxide formed in the substrate. Although the U.S. Pat. No. 3,972,754 process provides deep dielectric isolation, the oxide hump formation problem remains and, in addition, the process becomes more complicated because of the need for a second recessed oxide isolation. Indeed, due to normal mask tolerances, it is essentially impossible to perfectly align a second recess directly over a first recess. Furthermore, the epitaxial layer is relatively thick, for example, 2 to 4 microns, which in turn decreases device speed. Thus, the presence of the oxide hump adversely affects planarity, lowers the density of the circuit and, in general, slows device performance.
In addition, problems have developed in overall prior art procedures regarding the alignment of deposited metal with device contact areas. Device reliability and density suffer where a contact is not completely covered by metal and/or where, due to misalignment, it is necessary to provide an area of metal larger than contact area.